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What's New in Tanner Tools v15.1?

“The Corner Simulation entry is one the best features that Tanner added.  I use it extensively in my simulations, it's a huge time saver.”
 
              --Fred Floru, Principal Engineer, THAT Corporation, on T-Spice Pro v15

"Tanner Tools v15.10 incorporates many enhancements. The waveform viewing tool W-Edit is completely transformed, offers a more advanced display, and adds tcl scripting and a full range of features and built-in measurements. The speed upgrade to T-Spice, feature additions to L-Edit, and S-Edit, and Calibre compatible verification make Tanner Tools a great choice for Obsidian Technology."
 
              --Robert Heaton, General Manager, Obsidian Technology and v15.10 Beta User

play_button_for_homepage_smallWatch a video of our full flow tool suite -- HiPer Silicon v15

S-Edit Additions

  • Enhanced Connectivity views can be viewed and edited in SPICE format
                    -Spice, EDIF, and Verilog import now create Spice views
                    -Spice views are saved with the design and the imported Spice is saved
                    -Importing a hierarchical netlist creates separate cells for each subcircuit in the
                           netlist
  • Enhanced access control of designs allow better team collaboration
                    -Improved control over write permissions. When opening a design, users choose to
                              open the design with Exclusive or Non-Exclusive access
                                         »Opening a design with Exclusive Access means reserving the right to
                                            save a design and no-one else can write to it while the
                                            exclusive user has it open
                                         »Opening a design with Non-Exclusive Access means there is the
                                            possibility of writing to the design in the future,
                                            as long as no one else secures a write reservation before the attempt
                                            to save
  • Corner Simulation Setup to easily simulate across process corners, temperatures, etc.
                    -Corner Simulations can now be setup in the S-Edit Setup Spice Simulation dialog
                    -Parameters, Temperature, and libraries may be set to any value for each corner that
                              is defined
                    -Shows corner set up dialog filled in for library corners

Link to the S-Edit Datasheet

T-Spice Performance Improvements

  • 20% improvement Transient Simulation Performance (DC Convergence) due to new compiler and solver
  • Update of Verilog-A, SimKit, and BSIM4 SOI models

Link to the T-Spice Datasheet

W-Edit Enhancements

  • Histograms
                    -New Histogram chart type
                    -Results of .MEASURE commands in a Monte Carlo simulation are automatically
                              plotted on a histogram upon completion of the simulation

W-Edit_histogram
  • Eye diagrams

                    -New eye diagrams chart type

Eye_Chart

  • Performance Improvements

Learn more about W-Edit

L-Edit Productivity Gains

  • Wire drawing productivity enhancements greatly improve routing productivity
                     -Manual routing is much faster with improved via placement tools – end a wire,
                            place a contact, and start a new wire, all with one key stroke.
  • Object snapping to intersections
                     -Snapping to intersections operates on all objects (boxes, polygons, wires, circles)
                            and works through hierarchy

Link to the L-Edit Datasheet

HiPer DevGen Additions

  • Resistor Dividers

                     -Resistor generator has the ability to create resistor arrays

hiper_devgen_resistor_sm

  • HiPer DevGen cells now work better with SDL Router
                      -SDL is able to recognize resistors in a netlist that have the same L and W and
                              combine them into a single resistor array.

Learn more about the HiPer DevGen tool offering

HiPer Verify Enhancements

  • Major performance improvements for rules using Extent
  • Support for Size - Bevel option

Link to the HiPer Verify Datasheet

Download the What’s New in v15.10 Presentation to Learn More

Download the Supplemental What’s New in v15.11 Presentation

Contact Sales

Tanner Research Taiwan, Inc.

6F.-8, No. 8
Ziqiang S. Road
Jhubei City
Hsinchu County, 302, Taiwan
Phone: 886(03)-6579108
Fax: 886(03)-6579107

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